The invention relates generally to a method for fabricating a semiconductor device and, more specifically, to a technology of forming a floating body transistor used in a highly-integrated semiconductor device using a silicon-on-insulator (SOI) structure.
In many semiconductor device systems, a semiconductor memory device is configured to store data generated or processed in the device. For example, if a request from a data processor such as a central processing unit (CPU) is received, a semiconductor memory device may output data to the data processor from unit cells in the device, or the device may store data processed by the data processor to unit cells of an address transmitted with the request.
Although data storage capacity of semiconductor memory device has increased, the size of semiconductor memory device has not increased proportionally because various elements and components used for read or write operations in a semiconductor memory device have reduced in size. Accordingly, components and elements unnecessarily duplicated in the semiconductor memory device, such as transistors or wires, are combined or merged to decrease the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory device affects improvement of the degree of integration.
As an example of a semiconductor memory device, Dynamic Random Access Memory (DRAM) is a type of volatile memory device configured to retain data while a power source is supplied. The unit cell comprises a transistor and a capacitor. In the case of the unit cell having a capacitor, after the datum “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., the amount of the charge stored therein is reduced, because of both leakage currents generated at junction of the storage nodes and inherent characteristics of the capacitor. As a result, a refresh operation is periodically required on the unit cells so that data stored in the DRAM cannot be destroyed.
In order to prevent the reduction of charge, numerous methods for increasing capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node. For example, an insulating film used in a conventional capacitor, e.g., an oxide film, may be replaced with an advanced insulating film which has a larger dielectric constant, such as a nitrified oxide film or a high dielectric film. Otherwise, a capacitor having a two-dimensional structure is replaced with a three-dimensional cylindrical structure or a trench structure, thereby increasing the surface area of both electrodes of the capacitor.
As the design rule is reduced, the plane area where a capacitor can be positioned is reduced, and it is difficult to develop materials constituting an insulating film in the capacitor. As a result, the junction resistance value of the storage node SN and the turn-on resistance value of the transistor in the unit cell are larger, and accordingly it is difficult to perform normal read and write operations, and refresh characteristics deteriorate.
To improve the above-described shortcomings, the unit cell may comprise a transistor having a floating body. Thus, the unit cell of the semiconductor memory device does not include a capacitor used for storing data, but stores data in a floating body of the transistor included in the unit cell.
FIG. 1 is a cross-sectional diagram showing a method for storing a datum “1” in a conventional floating body transistor.
As shown, the floating body transistor is formed on a silicon-on-insulator (SOI) substrate that includes a bottom semiconductor layer 110, a buried insulating layer 120, and an upper silicon layer 130. A gate pattern 140 is formed on an active region defined on the upper silicon layer 130, and source and drain of the floating body transistor is formed by injecting a dopant into both sides of the gate pattern 140 in the upper silicon layer 130 through an ion-implantation process.
When the datum “1” is delivered through a bit line BL, a positive voltage is supplied to gate and drain of the floating body transistor (VG>0, VD>0) and a ground voltage GND (0V) is supplied to source of the floating body transistor. In order to store data in the floating body, a voltage level supplied on the word line is reduced by ½ or ⅓ of the voltage level applied to the bit line connected to one active region of the transistor, thereby generating hot carriers. Accordingly, a large amount of hot carriers are generated at a junction region of the bit line BL. Then, electrons are sent out into the bit line BL but holes remain in the floating body FB.
FIG. 2 is a cross-sectional diagram showing a method for storing a datum “0” in the conventional floating body transistor.
As shown, a negative voltage is supplied to the drain of the floating body transistor when the datum “0” is delivered (VD<0). At this time, voltage levels supplied with the gate and the source of the floating body transistor are same as the levels when the datum “1” is delivered. However, because of the negative voltage when the datum “0” is delivered, the hot carriers are not generated in the junction region, so that holes do not remain in the floating body FB.
Referring to FIGS. 1 and 2, amount of holes stored in the floating body FB is changed according to voltage level supplied to the drain of the floating body transistor through the bit line. The holes kept in the floating body lower the threshold voltage of the transistor of the unit cell; as a result, the amount of current flowing through the transistor increases. That is, the amount of current flowing when the holes are stored in the floating body of the transistor is larger than that flowing when no holes are stored. As a result, it is possible to distinguish whether the datum “1” or “0” is stored in the unit cell. That is, the unit cell can store the datum without any capacitor.
FIG. 3 is a layout and cross-sectional diagram illustrating a cell array configured as a floating body cell transistor in a general semiconductor memory device. As shown in FIG. 3, the cell array comprises a line-type active region 332, a bit line 360 over an active region, a source line 350 positioned at an intersection with the active region 332, and a word line 342. The semiconductor memory device including the floating body cell transistor is fabricated by using not a silicon bulk substrate but a SOI substrate that includes a bottom semiconductor substrate (not shown), a buried insulating film 320 and a top silicon layer 330.
In detailed, the line-type active region 332 is formed over the top silicon layer 330. A gate pattern 340 includes the word line 342 formed at the intersection with the active region. The cell array comprises a source line contact 352, a bit line contact 362, the gate pattern 340, and an interlayer insulating film 370 for electrically isolating the source line contact 352 and the bit line contact 362. The source line contact 352 and the bit line contact 362 are configured to respectively connect each of the source line 350 and the bit line 360, which are located between the gate patterns 340 that include the word line 342, to the active region 332 where the source and drain regions of the floating body cell transistor are located.
FIG. 4 is a circuit diagram illustrating an equalizing circuit of the cell array of FIG. 3.
As shown, neighboring floating body cell transistors A and B which are included as a unit cell in the cell array is connected to the same source line SL0 which is corresponded to the source line 350 shown in FIG. 3, and are respectively connected to different bit lines BL0 and BL1 which are matched with the bit lines 360 connected to the silicon layer 330 through the different bit line contacts 362.
As mentioned above, the cell array including the floating body cell transistor that shares the source line 350 over the line-type active region 332 may have an advantage of decreasing a chip size and simplifying the manufacturing process. However, when the unit cell where datum is delivered shares the source line 350 with the neighboring other unit cell, storing the datum in the unit cell the neighboring unit cell can have a bad effect to the other neighboring unit cell. That is, storing data in the unit cell can distort or destroy a datum already stored in the neighboring other unit cell. If the datum in the neighboring other unit cell is distorted, it is impossible to guarantee stable operations of the semiconductor memory device.
FIG. 5 is a table illustrating a write operation of the cell array of FIG. 4.
As shown, when data “1” and “0” are stored in a first unit cell A, a data error occurs in a second unit cell B as shown in FIG. 5.
In detail, in order to store the data “1” in the first unit cell A, a voltage of 0.8V is applied to a word line WL0, and a voltage of 1.6V is applied to a drain connected to a bit line BL0. Although the voltage of 0.8V is applied to a gate of the floating body cell transistor in a third unit cell C connected to the first unit cell A through the same word line WL0, no signal is delivered to a bit line BL1. In case of the third unit cell C, the data stored in a floating body are not affected because there is no voltage difference between the source and the drain although a voltage is applied to the gate.
In case of the second unit cell B being connected to the first unit cell A through the same bit line BL0 and the same source line SL0, although a voltage is not applied to the gate, a voltage difference is generated between the drain connected to the bit line BL0 and the source connected to the source line SL0. Although a voltage is not applied to a gate of the second unit cell B, a retention time of the data stored in the floating body is reduced by the voltage difference between the drain and the source. The reduction phenomenon of the retention time is sufficiently described in the International Academic Paper (“A capacitor-less DRAM cell on 75 nm gate length, 16 nm thin fully depleted SOI device for high density embedded memories,” Ranica, R. et al., Electron Devices meeting, 2004. IEDM Technical Digest. IEEE International Volume, Issue, 13-15 Dec. 2004. pp. 277-280).
In similar way, when the data “0” is stored in the first unit cell A, the voltage of 0.8V is applied to the gate, and a voltage of −0.8V is applied to the drain connected to the bit line BL0. Since the source line SL0 maintains a voltage of 0V, holes stored in the floating body are removed by a potential difference generated between the source and the drain. However, a relative potential difference is generated in the gate and the source although the voltage of −0.8V is applied only to the drain through the same bit line BL0. Referring to FIG. 5, if the drain of the second unit cell B to receive the voltage of −0.8V is 0V, the same effect as when 0.8V is applied to the source and the gate of the second unit cell B occurs. As a result, hot carriers are generated in the second unit cell B so that a data value stored in the second unit cell B may be changed.
As above described, in a semiconductor memory device having the conventional structure of a cell array including a unit cell configured as a floating body cell transistor over a SOI substrate, the data may be changed or destroyed in a neighboring unit cell whenever data are delivered and stored in a specific unit cell. As a result, the operation stability of the semiconductor memory device including the unit cell configured as the floating body cell transistor is degraded.